崛智科技 | 新竹 | Design for Efficiency | DFE | Process & Design Co-optimization

軟硬體研發設計 | near-Vt | EDA

Key Methodology Offering

崛智科技 | 新竹 | Design for Efficiency | DFE | Process & Design Co-optimization

Key Methodology Offering

IP Solution

  • Comprehensive near-VT solution (custom cell/SRAM)
  • Process monitor & timing/power management
  • Custom high-speed IF (PLL/LDDR4/MIPI)
  • AI modeling, compression/optimization & NN accelerator (RISC-V ISA extension)

ASIC Design Service

  • Agile timing re-K, design recipe & SPICE Monte accurate sign-off
  • Process diagnosis, WAT/FT correlation & design/process recipe optimization
  • Physical design, custom design methodology/flow & in-house utilities

Machine-learning Framework

  • Design metric (cell usage & PPA throughout design flows/design recipes)
  • WAT-aware timing model & sign-off recipe
  • Proprietary PCM, process tracking & post-silicon tuning

崛智科技 | 新竹 | Design for Efficiency | DFE | Process & Design Co-optimization

軟硬體研發設計 | near-Vt | EDA

崛智科技 | 新竹 | Design for Efficiency | DFE | Process & Design Co-optimization