Late Breaking Results
崛智科技 | 新竹 | Design for Efficiency | DFE | Process & Design Co-optimization
Late Breaking Results: Design Dependent Mega Cell Area and Power Optimization
Design Flow Optimize All But Library Cell?
- Library cell is key to timing, power and area optimization
- Ensures synthesizable design flow
- Conventionally, apply technology mapping, restructure, gate sizing, Vt swapping, or buffer insertion to translate RTL into netlist and meet design requirement.
- Traditional approach emphasize synthesis and P&R optimization ability
- without considering library cell (functional layout)quality
Predictably Mergeable Fully Layout Pattern
- Deterministic synthesis and placement approach, driven by
- Library cell, Floorplan, Timing/power constraint ® fixed
- Same approach ® same PPA result
- Merging scheme: physical location
- Additional slew buffer(non-location aware)
- Location aware merging, buffer free
- Without extra driving effort
- Without extra driving effort
- Additional slew buffer(non-location aware)
Mega Cell: Combine Synthesis & Custom Layout Niche
- Key: through placement analysis, find out re-layout candidate pattern
- Mega cell methodology
- Parallel scan line check placement result
- Provide library cell candidate list
- Re-layout mega cell
- Swap candidate cell into mega cell
Placement Aware Buffer Free Mega Cell
- Method1: pure physical merge
- Possible share items
Common device: power/ground
Reduction: useless layout space, area
- Method2: physical & logical function merge
- Possible share items
Common device: power/ground, same input gateReduction:
Function gate, power/timing
Useless layout space, area
Candidate Pattern to Mega Cell
(Samsung process full adder under distance constraint)
- Merge approach: N original cell into one mega cell
Method1: pure physical merge
Method2: physical & logical function merge
Experimental Results
- Environment setting
- Language: C++ with Tcl
- Platform: Xeon Linux workstation with 2.1GHz CPU and 128GB memory
All Methods Area and Power Compare
ckt1 compares 4 method in area/power
under different merging distance
Comparison with conventional approach(C.A.)
using M3 approach
Conclusion
- Mega cell combines full custom layout & synthesis benefit
- Aggressively shrink area/power
Q & A
1Can geometry scan line algorithm cover all candidate pairs?
- Yes, because overlapping scan approach can find all neighbor relating cells.
- By using parallel computing, the algorithm run time will be dramatically improved.
2Any other candidate pattern of SHA256?
Yes.
3Can mega cell approach apply on general design?
Yes, through geometry and logical connection analysis to find the candidates
- Arithmetic circuit(RISC-V, FPU): full adder, half adder
- Encoding/decoding circuit(avi/mpeg4 decoder): AOI/OAI